AL4V93/95 16k, 64k-bit line fifo applications - multimedia system - video line capture - tbc(time base corrector) - hard disk cache memory - anti-skip audio data buffer description the AL4V93/95 series memory products are high-performance, low-power 9-bit read/write fifo (first-in-first-out) memory chips. they are specially designed to buffer high speed streaming data for a wide range of data buffering applications, such as optical disk data caching, video line data buffering. ordering information part number AL4V93, al4v95 package 32-pin plastic tqfp and plcc power supply +3.3v 10% tqfp package top view averlogic al4v9x x-xx-xx xxxx xxxx 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 features ? high performance, low-power, fifo(first- in first-out) memory ? 2k x9 bit i/o port (AL4V93) ? 8k x9 bit i/o port (al4v95) ? high clock speed (100mhz) ? fully independent read/write access ? output enable control (data skipping) ? 3.3v 10% power supply with 5v tolerant ? standard 32-pin tqfp
a ver l ogic t echnologies , i nc . tel : 1 408 361-0400 e-mail: sales_usa@averlogic.com url: www.averlogic.com a ver l ogic t echnologies , c orp . tel : 886 2-87523988 e-mail: sales@averlogic.com.tw url: www.averlogic.com.tw october 30, 2004 (2k, 8k) x9 memory array input buffer output buffer write control logic read control logic timing & logic control write pointer read pointer offset regissers input data bus output data bus /oe wclk /wen rclk /ren al4v9x fifo block diagram /wrst /rrst the 9-bit input and output ports operate independently at a maximum speed of 100mhz. the built-in address decoder and pointer managing circuits provide a straightforward bus interface to serially read/write memory that reduces inter-chip design efforts. the al4v9x embedded memory array and high performance process technologies with extended controller functions (read skip, fixed and programmable status flags... etc.) offer flexible memory management. the input data is synchronous with a free- running clock (wclk), and input-enable pins (/wen). data is written into the fifo on every clock when enable pins are asserted. the output is synchronous with the other free- running clock (rclk) and enables (/ren). an output enable pin (/oe) is provided at the read port for tri-state control of the output port. the al4v9x series are operating in 3.3v power supply with 5v signal tolerant input. these chips are available as a 32-pin tqfp package. d istributed by :
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